1. Field of the Invention
The present invention relates to a semiconductor device comprising a bonding pad, and manufacturing method thereof.
2. Description of the Related Art
In recent years, the importance of the presence of a flip chip semiconductor device, which is utilized as a semiconductor device that is capable of achieving high-density assembly, is increasingly recognized. The flip chip semiconductor device comprises a flip-chip semiconductor chip and a multi-layer interconnect substrate having the chip mounted thereon. The flip-chip semiconductor chip comprises a bump having a protruded geometry, which contains metals having lower melting point such as solder, gold or the like, formed on the surface of the semiconductor chip. The multi-layer interconnect substrate comprises an electrode pad having a pattern that is same as the bump arrangement pattern.
When a bump is formed in such flip-chip semiconductor chip, a technology called Under Bump Metal (UBM), in which a polyimide film is provided on an electrode pad and an electrode is formed in the opening thereof, and then a solder ball is compressively bonded onto the electrode, is widely adopted for the purpose of preventing the generation of the crack in the solder during the heat cycles in the operation of the semiconductor device.
In order to prevent a dishing (a phenomena, in which a film thickness between a convex part and another convex part becomes thinner after conducting a polishing) occurred in a pad portion, technologies of providing an area consisting of an insulating material having an island shape or a slit shape is known. These technologies are disclosed in, for example, Japanese Patent Laid-Open No. H10-229,085 (1998) and Japanese Patent Laid-Open No. H11-150,114 (1999).
FIGS. 1A and 1B are schematic diagrams illustrating a conventional bump structure that utilizes the technology described above. FIG. 1A shows a plan view of a bump portion, and FIG. 1B is a cross sectional view thereof along a line AA′ shown in FIG. 1A. A TiN film 104 is formed on an upper surface of a pad part 100 comprising a Cu pad area (a metal area) 101 and an insulating area 102, and a SiON film 106 and a polyimide film 108 are formed on the upper surface thereof in this sequence. An opening having a bottom surface of the TiN film 104 is provided on the SiON film 106 and the polyimide film 108. A multi-layered film 110 having TiW and Cu formed thereon in this sequence and a barrier metal film 120 comprising Ni film 112 and Cu film 114 are formed in the opening.
FIGS. 2A to 2D and FIGS. 3E and 3F are cross sectional views of the bump structure, illustrating the processes for forming the bump structure shown in FIG. 1. First, as shown in FIG. 2A, a pad portion 100 comprising a Cu pad area 101 and an insulating area 102 is formed as an uppermost layer of the multi-layer interconnect via a damascene process. The entire surface is not composed of the Cu pad area 101, and instead the insulating area 102 is provided therein to inhibit occurring of the dishing in the pad portion.
Then, radio frequency (RF) etching is conducted to etch a Cu oxide film formed on the surface of the Cu pad area 101 off, and thereafter the TiN film 104 is deposited via sputtering. A photo resist is applied over the TiN film 104 and exposed to light, and then the unwanted TiN film 104 is removed by dry etching process to form a pad and a fuse. This status is shown in FIG. 2B.
Subsequently, as shown in FIG. 2C, a SiON film 106 is formed on the TiN film 104, and thereafter a pad via 107 is opened as shown in FIG. 2D. The pad via 107 is formed so that almost entire area, on which the pad portion 100 is formed, is exposed.
Then, a polyimide film 108 is formed over the TiN film 104 and the SiON film 106 via an application process, and after that, exposure thereof is carried out to form an opening 109 on the pad portion 100 (FIG. 3E). Then, as shown in FIG. 3F, a cure process is conducted at a temperature of 400 degree C. for 10 minutes to form a cured polyimide film 108′. Thereafter, a multi-layered film 110 having TiW and Cu deposited in this sequence is formed in the opening by using a sputter process, and then the unwanted multi-layered film 110 is removed. A Ni film 112 and a Cu film 114 are formed on the multi-layered film 110 via a selective plating (FIG. 4). As described above, the bump structure comprising the barrier metal film 120 formed on the pad portion 100 via the TiN film 104 therebetween is completed. The related prior art documents are: Japanese Patent Laid-Open No. H10-229,085 (1998); and Japanese Patent Laid-Open No. H11-150,114 (1999).
However, according to the investigations of the present inventors, it was confirmed that the above-described process provides insufficient adhesion at an interface between the TiN film 104 and the barrier metal film 120, or generates flakes 132 as shown in FIG. 4. In other words, when the constitution of providing an area (insulating area 102) that consists of an insulating material in the pad is employed in order to prevent a dishing in the pad portion, such constitution may cause a new problem of generating a poor adhesion at the interface.